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<div class="title">xycrcb2rgb_hw.h File Reference</div>  </div>
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Macros</h2></td></tr>
<tr class="memitem:ga9e810d9723caf0b5d13e0461e3cc037c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__ycrcb2rgb__v7__0.html#ga9e810d9723caf0b5d13e0461e3cc037c">XYCrCb2Rgb_ReadReg</a>(BaseAddress,  RegOffset)&#160;&#160;&#160;<a class="el" href="group__ycrcb2rgb__v7__0.html#ga85572c7452cd40a0b62b2e8124472152">XYCrCb2Rgb_In32</a>((BaseAddress) + (u32)(RegOffset))</td></tr>
<tr class="separator:ga9e810d9723caf0b5d13e0461e3cc037c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga2e7e4b983842e5d2b75bba8ee58cc763"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__ycrcb2rgb__v7__0.html#ga2e7e4b983842e5d2b75bba8ee58cc763">XYCrCb2Rgb_WriteReg</a>(BaseAddress,  RegOffset,  Data)&#160;&#160;&#160;<a class="el" href="group__ycrcb2rgb__v7__0.html#ga1d3f7d143618eefcb171ebde55553dfd">XYCrCb2Rgb_Out32</a>((BaseAddress) + (u32)(RegOffset), (Data))</td></tr>
<tr class="separator:ga2e7e4b983842e5d2b75bba8ee58cc763"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Control Registers</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>Control Registers offset for YCRCB2RGB core. </p>
</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">Timing Control Registers</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>Timing control registers offset for YCRCB2RGB core. </p>
</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">Core Specific Registers</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>Core specific registers offset </p>
</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">Control Register Bit Masks</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>Control Register bit definition for YCRCB2RGB core. </p>
</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">Slave Error Bit Masks</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">Interrupt Register Bit Masks</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>Interrupt Register bit definition for YCRCB2RGB core.</p>
<p>It is applicable for STATUS and IRQ_ENABLE Registers. </p>
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<tr><td colspan="2"><div class="groupHeader">Version Register Bit Masks and Shifts</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">Active Size Register Bit Masks and Shifts</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">RGBMAX Register Bit Mask</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">RGBMIN Register Bit Mask</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">ROFFSET Register Bit Mask</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">GOFFSET Register Bit Mask</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">BOFFSET Register Bit Mask</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">A ,B, C , D Coefficient Register Bit Mask</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">General purpose Bit Mask and Shifts</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">Data widths in bits per color.</div></td></tr>
<tr class="memitem:ga214fd3c975c68cb2ca7988817371c8c7"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__ycrcb2rgb__v7__0.html#ga214fd3c975c68cb2ca7988817371c8c7">XYCC_DATA_WIDTH_8</a>&#160;&#160;&#160;8</td></tr>
<tr class="separator:ga214fd3c975c68cb2ca7988817371c8c7"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaaec9a2fa2ddb4894e142b707a751bf07"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__ycrcb2rgb__v7__0.html#gaaec9a2fa2ddb4894e142b707a751bf07">XYCC_DATA_WIDTH_10</a>&#160;&#160;&#160;10</td></tr>
<tr class="separator:gaaec9a2fa2ddb4894e142b707a751bf07"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gab5c614a9911130d0e63959f5177dbe19"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__ycrcb2rgb__v7__0.html#gab5c614a9911130d0e63959f5177dbe19">XYCC_DATA_WIDTH_12</a>&#160;&#160;&#160;12</td></tr>
<tr class="separator:gab5c614a9911130d0e63959f5177dbe19"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaf1725dae672e5d9a3af8304e59446ae1"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__ycrcb2rgb__v7__0.html#gaf1725dae672e5d9a3af8304e59446ae1">XYCC_DATA_WIDTH_16</a>&#160;&#160;&#160;16</td></tr>
<tr class="separator:gaf1725dae672e5d9a3af8304e59446ae1"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Backward Compatibility Macros</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>To support backward compatibility, following macros definition are re-defined. </p>
</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">Interrupt Registers</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>Interrupt status register generates a interrupt if the corresponding bits of interrupt enable register bits are set. </p>
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